Use only the lowest 32 bit of input for 32 bit division operations #100
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refcell
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Jan 6, 2025
Thanks! Added in 0749a92 |
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## master #100 +/- ##
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Coverage 61.89% 61.89%
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Files 27 27
Lines 4091 4091
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Hits 2532 2532
Misses 1427 1427
Partials 132 132 ☔ View full report in Codecov by Sentry. |
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Description
The RISCV implementations (sol/fast/slow) return incorrect results, in conflict with the RISCV specification, for all 32-bit division operations (DIVW, DIVUW, REMW, REMUW) when the divisor is zero.
All word (32-bit) arithmetic operations are supposed to take as its operands only the lowest 32 bits of the input registers.
However, in the division by zero code that requirement fails.
Observe that the switch statement only catches the case in which the input register has all bits set to zero. In reality, only the least significant 32 bits should be considered.
In the case any of the most significant 32 bits is set, the
switchstatement will follow the default path, and the division will be performed with the same behavior as an EVM division (except for sign extending) -- that means the division by zero will result in a zero result, instead of the correct RISCV one (all bits set for division, or the original numerator for remainder).Mask the input before the switch statement.